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| 0.5 W POWER PHEMT * FEATURES 28 dBm Output Power at 1-dB Compression at 18 GHz 10 dB Power Gain at 18 GHz 24 dBm Output Power at 1-dB Compression at 3.3V 55% Power-Added Efficiency DRAIN BOND PAD SOURCE BOND PAD (2x) GATE BOND PAD LP750 * DESCRIPTION AND APPLICATIONS The LP750 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam directwrite 0.25 m by 750 m Schottky barrier gate. The recessed "mushroom" gate structure minimizes parasitic gate-source and gate resistances. The epitaxial structure and processing have been optimized for reliable high-power applications. The LP750 also features Si3 N4 passivation and is available in a variety of packages, including SOT89 and P100 packages. Typical applications include commercial and other types of high-performance power amplifiers, including use within SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. DIE SIZE: 12.6X16.9 mils (320x430 m) DIE THICKNESS: 3 mils (75 m) BONDING PADS: 3.3X2.4 mils (85x60 m) * ELECTRICAL SPECIFICATIONS @ TAmbient = 25C Parameter Saturated Drain-Source Current Power at 1-dB Compression Power Gain at 1-dB Compression Power-Added Efficiency Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Magnitude Gate-Drain Breakdown Voltage Magnitude Thermal Resistivity frequency=18 GHz Symbol IDSS P-1dB G-1dB PAE IMAX GM IGSO VP |VBDGS| |VBDGD| JC Test Conditions VDS = 2 V; VGS = 0 V VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS; PIN = 10 dBm VDS = 2 V; VGS = 1 V VDS = 2 V; VGS = 0 V VGS = -3 V VDS = 2 V; IDS = 4 mA IGS = 4 mA IGD = 4 mA -0.25 -12 -12 180 Min 180 26.5 8 Typ 225 28 10 55 400 230 5 -1.2 -15 -16 65 40 -2.0 Max 265 Units mA dBm dB % mA mS A V V V C/W Phone: (408) 988-1845 Fax: (408) 970-9950 http:// www.filss.com Revised: 2/26/01 Email: sales@filss.com 0.5 W POWER PHEMT * ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power Channel Operating Temperature Storage Temperature Total Power Dissipation Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Test Conditions TAmbient = 22 3 C TAmbient = 22 3 C TAmbient = 22 3 C TAmbient = 22 3 C TAmbient = 22 3 C TAmbient = 22 3 C -- TAmbient = 22 3 C -65 Min Max 12 -4 2xIDSS 7.5 300 175 175 2.2 Units V V mA mA mW C C W LP750 Notes: * Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. * Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Absolute Maximum Power Dissipation to be de-rated as follows above 25C: PTOT= 2.2W - (0.015W/C) x THS where THS = heatsink or ambient temperature. * HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A (0-500 V). Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. ASSEMBLY INSTRUCTIONS The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. * * All information and specifications are subject to change without notice. Phone: (408) 988-1845 Fax: (408) 970-9950 http:// www.filss.com Revised: 2/26/01 Email: sales@filss.com |
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